feat(privshield): E2E hardware program — validated C core + multi-provider firmware scaffolds

Take VEIL from the synthetic Rust reference model toward real WiFi silicon
across multiple hardware providers, around one shared, host-validated core.
Answers the questions "can OpenWRT / open WiFi software implement this?" and
"can ESP32 help scramble signals?" with an honest per-platform feasibility map.

Portable C shield core (firmware/privshield/core/) — VALIDATED (host test):
- veil_shield.{h,c}: keyed Givens-rotation obfuscation of the identity-bearing
  "fine" subspace, C99, no malloc / no libc I/O, only <math.h>. SplitMix64 key
  schedule byte-identical to the Rust crate, so on-air behavior is consistent
  everywhere and every adapter links the same math.
- make test passes: energy conservation (orthogonal => "not jamming"),
  reversibility (recover inverts apply), wrong-key-fails, and PRNG stream parity
  with the Rust crate. This is build/host evidence, NOT silicon.

Per-provider adapters (all SYNTHETIC / L0, build-only, TODO(hw) markers):
- openwifi/  grade B (ceiling A, effort D): only open PHY/MAC (FPGA) that can
  host the full keyed rotation + inverse; needs new HDL + 2nd TX chain. Carries
  the P5 measurement protocol (MEASUREMENT.md) for the first MEASURED result.
- openwrt/   grade C: per-packet keyed unitary is blob-blocked on commodity APs;
  coarse compliant knobs (TX antenna map, sounding-cadence jitter) reachable
  from userspace/hostapd; ath9k is the one credible driver-patch route.
- nexmon/    grade C: reading the compressed-BF angles is solved (nexmon_csi /
  Wi-BFI); shaping the transmitted report is research-grade (D11 ucode-adjacent).
- esp32/     grade F (self) / B (supporting): cannot shape its own BF feedback
  (closed esp-phy-lib blob); legitimate as a sensing detector and external-RIS
  controller — the honest way ESP32 "helps scramble", via an external surface.

Docs:
- firmware/privshield/README.md: architecture, layout, and the feasibility matrix.
- ADR-290: the E2E hardware program, PROOF discipline, and per-provider decision;
  added to docs/adr/README.md index.

Compliant waveform controls only, never jamming. No adapter has run on silicon;
no MEASURED claim is made (that is roadmap P5, gated on a captured log).

Co-Authored-By: claude-flow <ruv@ruv.net>
Claude-Session: https://claude.ai/code/session_01WEXNqzs7UsfNFBcP5yW21p

firmware/privshield/esp32/veil_ris_controller/include/veil_ris_controller.h

@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: MIT OR Apache-2.0
+ *
+ * veil_ris_controller — drive an EXTERNAL reconfigurable intelligent surface
+ * (RIS) to obfuscate the sensing-direction channel.
+ *
+ * STATUS: SYNTHETIC / L0. Build-only ESP-IDF component skeleton. Never flashed,
+ * never captured on silicon. No RIS hardware exists in this repo. Do NOT claim
+ * runtime or on-air behavior without a captured hardware log.
+ *
+ * WHY THIS EXISTS (honest framing): the ESP32 cannot shape its own transmitted
+ * beamforming feedback — the precoding / compressed-BF-report path lives in the
+ * closed Espressif Wi-Fi PHY blob (esp-phy-lib) and is not modifiable (see
+ * README.md). The legitimate, compliant way an ESP32 can "help scramble" a
+ * sensing signal is to act as the *controller for a separate passive surface*:
+ * a RIS whose per-element phase states are switched over time. Following the
+ * PrivISAC pattern (arXiv:2601.04488), each element is toggled between two
+ * states chosen so the surface's response is ~identical in the *communication*
+ * direction (throughput preserved) but differs sharply in the *sensing*
+ * direction (an eavesdropper's channel is perturbed). The ESP32 is a GPIO/SPI
+ * pin-driver here; it emits no RF of its own.
+ *
+ * The state schedule is *keyed* and deterministic: it is drawn from the
+ * portable core's `veil_rng` (SplitMix64), so an associated / authorized
+ * sensor holding the same key can reconstruct — and thus tolerate — the
+ * schedule, while an unauthorized observer cannot.
+ */
+#ifndef VEIL_RIS_CONTROLLER_H
+#define VEIL_RIS_CONTROLLER_H
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stddef.h>
+#include "esp_err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* How the surface's element bits are clocked out. */
+typedef enum {
+    VEIL_RIS_IFACE_GPIO = 0, /* small surfaces: one GPIO per element / bank */
+    VEIL_RIS_IFACE_SPI,      /* larger surfaces: shift-register / driver IC */
+} veil_ris_iface_t;
+
+typedef struct {
+    veil_ris_iface_t iface;
+
+    /* Number of independently switchable RIS elements (or 1-bit banks). */
+    size_t   n_elements;
+
+    /* Keyed, deterministic schedule (shared with the associated receiver). */
+    uint64_t key;
+
+    /* Dwell time per configuration, microseconds. Must be short vs. the
+     * channel coherence time to spread perturbation across the sensing burst,
+     * yet long enough for the surface's switching diodes to settle. */
+    uint32_t dwell_us;
+
+    /* GPIO backend: one pin per element (n_elements <= number of pins). */
+    const int *gpio_pins;    /* borrowed; length == n_elements               */
+
+    /* SPI backend: bits are packed MSB-first into ceil(n_elements/8) bytes and
+     * shifted out per configuration. */
+    int      spi_host;       /* e.g. SPI2_HOST                               */
+    int      spi_cs_gpio;    /* latch / chip-select                          */
+    int      spi_clock_hz;   /* driver-IC clock                             */
+} veil_ris_controller_cfg_t;
+
+/* Initialize the chosen interface. Registration only — says nothing about a
+ * physical surface actually switching. */
+esp_err_t veil_ris_controller_init(const veil_ris_controller_cfg_t *cfg);
+
+/* Compute the next keyed configuration bitmap and clock it to the surface.
+ * `out_bits` (optional, may be NULL) receives the packed bitmap for tests.
+ * `out_len` is the byte length of `out_bits` on input. The bit pattern is
+ * derived purely from `veil_rng` + the PrivISAC two-state assignment, so it is
+ * reproducible from (key, step_index). */
+esp_err_t veil_ris_controller_step(uint8_t *out_bits, size_t out_len);
+
+/* Start/stop a periodic timer that calls _step() every dwell_us. */
+esp_err_t veil_ris_controller_start(void);
+esp_err_t veil_ris_controller_stop(void);
+
+/* Monotonic count of configurations applied since init (telemetry/tests). */
+uint64_t veil_ris_controller_step_count(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* VEIL_RIS_CONTROLLER_H */