Commit Graph
4 Commits
Author SHA1 Message Date
ravenandGiotta Simon de87095cbc Add front and rear image for HPE ProLiant DL360 Gen9 (#2297)
* Add front and rear image for HPE ProLiant DL360 Gen9

* Fix typos while we are at it.

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Co-authored-by: Giotta Simon <simon.giotta@ruag.ch>
2024-10-13 22:05:16 +01:00
ravenandGiotta Simon bdb9085185 Add FS FHD-FAP Modules and Image for FHD-FPP5DRL Device (#2303)
* Add 12 and 18 Port FS FHD-FAP Modules

* add elevation image for FHD-FPP5DRL

* Fix pre-commit findings.

* FHD-1UFCE is not full depth

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Co-authored-by: Giotta Simon <simon.giotta@ruag.ch>
2024-08-22 12:16:44 -04:00
ravenandGiotta Simon 377d0c3b06 Add generic LSH/APC patchpanels with 24 and 48 ports. (#2304)
* Add generic LSH/APC patchpanels with 24 and 48 ports.

* Fix Pytest findings.

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Co-authored-by: Giotta Simon <simon.giotta@ruag.ch>
2024-08-22 12:07:52 -04:00
ravenandGiotta Simon 5f2b11b8aa Make Cable Management Panel Models Human Readable (#2306)
* remove old files

* Make model human readable and rename 'ru' to 'U' to match other devices.

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Co-authored-by: Giotta Simon <simon.giotta@ruag.ch>
2024-08-22 12:02:56 -04:00